Method and apparatus for fabricating cmos field effect transistors

ABSTRACT

A method of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors which includes selective doping and full silicidation of a polysilicon material comprising the gate electrode of the transistor. In one embodiment, prior to silicidation, the polysilicon is amorphized. In a further embodiment, siliciding is performed at a low substrate temperature.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 10/669,898, filed Sep. 24, 2003, which is herein incorporatedby reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a method for fabricatingdevices on semiconductor substrates. More specifically, the presentinvention relates to a method of fabricating complementary metal oxidesemiconductor (CMOS) field effect transistors on a semiconductorsubstrate.

2. Description of the Related Art

Integrated circuits (ICs) may include more than one millioncomplementary metal oxide semiconductor (CMOS) field effect transistorsthat are formed on a semiconductor substrate and are wired together intocircuits to perform various functions within the IC. A CMOS transistorcomprises a gate structure disposed between source and drain regionsthat are formed in a semiconductor material. The gate structuregenerally comprises a gate electrode and a gate dielectric. The gateelectrode is disposed over the gate dielectric and controls a flow ofcharge carriers in a channel region between the drain and source regionsbeneath the gate dielectric to turn the transistor on or off.

In high-speed and high device density ICs, conventional gate structureshaving polysilicon gate electrodes are inefficient because of a freecarrier depletion layer in the polysilicon. In an ON state of the CMOStransistor, the depletion layer increases the effective thickness of thegate dielectric and, correspondingly, lowers capacitance of the gatestructure, thereby degrading operational performance of the transistor.

For example, a lower gate capacitance negatively impacts the performanceof the transistor. Specifically, high gate capacitance leads to a lowerVg-Vt (where Vg is the gate voltage and Vt is the threshold voltage) forthe same number of on-state carriers and thus decreasing transistorpower. Additionally, high gate capacitance also improves the scalinglength of the device making it possible to build a smaller transistor,which has a faster switching speed.

In advanced CMOS transistors, gate structures may comprise silicide gateelectrodes. In such gate structures, the polysilicon is converted to asilicide using a solid-state reaction with a metal or metallic alloy. Asilicide is an compound of Si and a metal. Herein, materials areconventionally identified using their chemical formulas. In the gatestructure, the silicide behaves like a metal and, as such, is able toeliminate the depletion effect.

However, it is desirable to have control over the effective workfunction of the metal-gate. The effective work function of the gatedetermines the threshold voltage of the transistor. A CMOS device iscomposed of two types of transistors; an n-type field effect transistor(nFET) and a p-type field effect transistor (pFET) each having adifferent threshold voltage and thus different workfunction. Theworkfunction of a metal is the energy necessary to remove an electron sothat it is no longer bound to the metal (the energy difference betweenthe vacuum level and Fermi level). For a CMOS device it is necessary tohave dual metal gates with the appropriate workfunctions for each typeof transistor.

Therefore, there is a need in the art for an improved method forfabricating CMOS field effect transistors in the manufacture ofintegrated circuits and for an improved method for controlling the workfunction of the metal-gate of a transistor.

SUMMARY OF THE INVENTION

In one embodiment, the present invention discloses a method offabricating complementary metal oxide semiconductor (CMOS) field effecttransistors that comprises selective doping and silicidation of apolysilicon material of a gate electrode of the transistor. In oneembodiment, the dopants include at least one of As, P, B, Sb, Bi, In,Tl, Al, Ga, Ge, Sn and N₂ In a further embodiment, prior tosilicidation, the polysilicon is amorphized. In yet another embodiment,silicidation is performed at a low substrate temperature.

Another aspect of the invention is a CMOS field effect transistor formedusing the inventive method.

BRIEF DESCRIPTION OF THE DRAWINGS

The teachings of the present invention can be readily understood byconsidering the following detailed description in conjunction with theaccompanying drawings, in which:

FIG. 1 depicts a flow diagram of a method for fabricating a CMOS fieldeffect transistor in accordance with one embodiment of the presentinvention;

FIGS. 2A-2E depict a series of schematic, cross-sectional views of asubstrate having the CMOS field effect transistor being fabricated inaccordance with the method of FIG. 1; and

FIG. 3 depicts an exemplary diagram illustrating a work function ofsilicide gate electrodes of CMOS field effect transistors fabricatedusing the method of FIG. 1.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures.

It is to be noted, however, that the appended drawings illustrate onlyexemplary embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

DETAILED DESCRIPTION

The present invention is a method for fabricating CMOS field effecttransistors comprising silicide gate electrodes having a pre-determinedand controlled work function. The method may be used to manufacture PMOSand NMOS transistors in ultra-large-scale integrated (ULSI)semiconductor devices and circuits.

FIG. 1 depicts a flow diagram for one embodiment of the inventive methodof fabricating CMOS field effect transistors as a method 100. The method100 includes the processes that are performed upon a film stack of thetransistor.

FIGS. 2A-2E depict schematic, cross-sectional views of a substrateshowing the CMOS field effect transistor being fabricated using themethod 100. The images in FIGS. 2A-2E are not depicted to scale and aresimplified for illustrative purposes. To best understand the invention,the reader should simultaneously refer to FIGS. 1 and 2A-2E.

The method 100 starts at step 101 and proceeds to step 102. At step 102,a polysilicon layer 204 (i.e., gate electrode layer) is formed upon agate dielectric layer 202 disposed on a substrate 200, e.g.,silicon-on-insulator (SOI) substrate (FIG. 2A). The SOI substrate 200conventionally comprises a buried oxide layer 201 sandwiched between asilicon-containing layer 203 and silicon (Si) wafer 205 (all shown inFIG. 2A only). The silicon-containing layer 203 may be formed from atleast one film of Si, SiGe, SiC, SiGeC, Si/SiGe, Si/SiC, Si/SiGeC, andthe like. Such SOI substrates 200 are known to those skilled in the art.The gate dielectric layer 202 generally comprises one or more films ofundoped and doped oxides, such SiO₂, SiON, Al₂O₃, ZrO₂, HfO₂, Ta₂O₃,TiO₂, silicates, perovskite-type oxides and mixtures thereof, amongother dielectric materials. The polysilicon layer 204 and gatedielectric layer 202 are generally formed to a thickness of about 400 to2000 and 10 to 100 Angstroms, respectively. The layers 204 and 202 maybe deposited using any conventional vacuum deposition technique (e.g.,physical vapor deposition (PVD), chemical vapor deposition (CVD), plasmaenhanced CVD (PECVD), atomic layer deposition (ALD), and the like).

At step 104, impurities (i.e., dopants) are embedded in the polysiliconlayer 204 (FIG. 2B). In one embodiment, step 104 performs an ionimplantation process that uses an ion beam 206 comprising a controlledamount of at least one of As, P, B, Sb, Bi, In, Tl, Al, Ga, Ge, Sn andN₂. In such an embodiment, the selectively controlled dose may be in arange between about 1×10¹⁴ and 5×10¹⁵ ions/cm². Preferably, when the ionbeam 206 comprises B, P As, and Sb, the dose is about (5-20)×10¹⁴,(5-25)×10¹⁴, (5-35)×10¹⁴, and (5-40)×10¹⁴ ions/cm², respectively. In afurther embodiment, P, As, Sb and Bi are used to dope the regions in thepolysilicon layer 204 where NMOS transistors are being fabricated on thesubstrate 200, while B and Ge is used to dope the regions where the PMOStransistors are being fabricated, respectively. After silicidation ofthe polysilicon layer 204 (discussed below in reference to step 110), P,As, Sb and Bi facilitate conduction band control, while B and Geimpurities provide valence band control in the silicided material ofgate electrodes of the transistors, respectively. In another embodiment,to obtain multiple work functions, lithographic masks may be used toexpose selected regions in the polysilicon layer 204 to the ion beam206. In an alternate embodiment, the impurities may be introduced using,e.g., a PVD or CVD process, either during step 102 or step 104.

At step 106, the polysilicon layer 204 is amorphized (FIG. 2C). In oneexemplary embodiment, to amorphize the polysilicon, step 106 performs anion implantation process that uses an ion beam 212 comprising acontrolled amount of at least one of Si and Ge. Amorphization of thepolysilicon may favorably increase impurity segregation at thepolysilicon/silicide interface (discussed below in reference to step110) of the impurities that were implanted, at step 104, in the layer204. In some applications, amorphization of the polysilicon layer 204 isnot needed and, as such, step 106 is considered optional.

At step 108, a gate structure 210 of the CMOS transistor beingfabricated is formed on the substrate 200. FIG. 2D depicts the gatestructure 210 that has been planarized using a chemical-mechanicalpolishing (CMP) process. The gate structure 210 may be formed usingknown methods in the art, e.g., lithographic, reactive ion etching,deposition, annealing, CMP, and other processes which are conventionallyused to fabricate CMOS transistors. Such processes are disclosed, forexample, in commonly assigned U.S. patent application Ser. No.10/300,165, filed on Nov. 20, 2002 (Attorney docket numberYOR920020183US1), which is incorporated herein by reference.

In one exemplary embodiment, the gate structure 210 comprises the gatedielectric layer 202, the polysilicon layer 204, raised source/drain(RSD) regions 216, insulative spacers 218 and 220, and a metallic layer208 that is deposited upon the polysilicon layer 204. The metallic layer208 may be formed from at least one of a metal and an alloy. The metalmay be at least one of Ni, Co, Pt, Ti, Pd, W, Mo, and Ta; and the alloymay comprise at least one of C, Al, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Ge,Zr, Nb, Mo, Ru, Rh, Pd, Ag, In, Sn, Hf, Ta, W, Re, Ir, and Pt. Aself-aligned silicide process (salicide) is used to consume the poly-Siof the gate electrode in a reaction with the metal layer to form asilicide metal gate electrode. The salicide process comprises thedeposition of a blanket metal layer, a first low temperature anneal toform the first phase of the silicide, a selective wet etch to remove thenon-reactive metal, and an optional second anneal at a highertemperature to form a lower resistance phase of the silicide (furtherdiscussed in step 110 in detail). In a further embodiment, the RSDregions 216 may be grown using a selective Si epitaxy process, implantedwith appropriate dopants, and then metallized to form a silicidecontact. In an alternate embodiment, the substrate 200 may be a Si wafercomprising drain and source regions of the CMOS transistor being formedthereon.

At step 110, the polysilicon layer 204 is converted to a silicide,thereby forming a silicide gate electrode 214 (FIG. 2E). In the depictedembodiment, during step 110, the polysilicon layer 204 and metalliclayer 208 are entirely consumed and replaced with the silicide. In analternate embodiment (not shown), a thickness of the metallic layer 208may be selected such that silicide gate electrode 214 is composed ofmultiple silicide layers where the top most layer is a more metal richsilicide phase compared to the bottom layer.

Silicidation of the polysilicon layer 204 may be performed using, forexample, an annealing process. In one exemplary embodiment, theannealing process is performed in atmosphere of at least one of an inertgas (e.g., He, Ar, and the like), N₂, and forming gas (i.e., solution ofabout (3-10)% of H₂ in N₂ or Ar). In a further embodiment, the annealingprocess for NiSi formation is performed at a pre-selected low substratetemperature (e.g., about 350 to 500 degrees Celsius) and for an extendedduration of time, such as about 0.3 to 30 min. In an additionalembodiment, the annealing process for CoSi₂ formation is performed at apre-selected low substrate temperature (e.g., about 450 to 750 degreesCelsius) and for an extended duration of time, such as about 0.3 to 30min. In another embodiment, the annealing process for PtSi and PdSiformation is performed at a pre-selected low substrate temperature(e.g., about 350 to 600 degrees Celsius) and for an extended duration oftime, such as about 0.3 to 30 min. Such an annealing process mayfavorably increase solubility and segregation of the impurities in thesilicide gate electrode 214 being formed, as well as lower the stress inthe gate dielectric layer 202 and increase adhesion between the layer202, electrode 214, and substrate 200. In one specific preferredembodiment, when the metallic layer 208 comprises Ni, the NiSi gateelectrode is formed using the annealing process performed in atmosphereof N₂, at 450 degrees Celsius, and for a duration of approximately 15min.

As the silicide forms, the implanted impurities tend to segregate into aboundary region between the silicide and the remaining polysilicon andare “plowed” towards the gate dielectric layer 202. When the silicidefront reaches the gate dielectric layer 202, the impurities become fixedat the interface between the silicide and the dielectric layer 202, thuschanging the workfunction of the gate structure 210, as well as electronmobility in the silicide gate electrode 214.

After the annealing process, the gate structure 210 comprises thesilicide gate electrode 214 formed upon at least one monolayer of theimplanted impurities that are disposed at an interface between thesilicide gate electrode 214 and gate dielectric layer 202. Segregationof the impurities within the gate structure may readily be observedusing, e.g., conventional secondary ion mass spectroscopy (SIMS)methodology.

In one exemplary embodiment, when the impurity was As, the workfunctionand the peak electron mobility of the NiSi gate structure 210 were about−250 eV closer to the conduction band in Si and 2-10% greater,respectively, than the corresponding workfunction and electron mobilityof the gate structure having a NiSi gate metal electrode formed fromundoped polysilicon.

The work function of the silicide electrode is defined by the amount(i.e., dose) and material of the impurity that, at step 104, wasimplanted in the polysilicon layer 204. In general terms, a change, orshift, in the value of work function of the silicide gate electrode 214is proportional to concentration of the impurities that are embedded inthe silicide (discussed below in reference to FIG. 3). Using acontrolled dose and material of the impurity, at step 104, the workfunction of the silicide gate electrode 214 may selectively be modifiedto specific values, such as the ones that facilitate pre-determinedthreshold voltages and optimal operation of the PMOS and NMOStransistors. In one exemplary embodiment, a threshold voltage (about0.4V) of the NiSi silicide gate electrode 214 was selectively modifiedby at least −0.25V using controlled doping of the polysilicon layer 204with As, as described above in reference to step 104. The correspondingmaximum shiftranges for selectively controlled threshold voltages of thesilicide gate electrode 214 doped with B, P, As and Sb were about 0.1V;0.2V; 0.25 and 0.5V, respectively.

Upon completion of the annealing process, at step 112, the method 100ends.

FIG. 3 depicts an exemplary graph 300 that illustrates dependence of thework function of the silicide gate electrode 214 from an amount of theimpurity in the gate electrode. Specifically, in FIG. 3, a shift 302(y-axis) in the work function of the gate electrode 214 is plottedversus a dose 304 of the impurity that, at step 104 of the method 100(discussed in reference to FIG. 1 above), was implanted in thepolysilicon layer 204. Herein, the shift 302 is expressed in the unitsof “eV” (electron-volt), the dose 304 is expressed in the units of“ions/cm²”, and exemplary traces 305-308 relate the B, P, As and Sbimpurities, respectively, in the NiSi gate electrode 214.

While the foregoing is directed to the illustrative embodiment of thepresent invention, other and further embodiments of the invention may bedevised without departing from the basic scope thereof, and the scopethereof is determined by the claims that follow.

1. A complementary metal oxide semiconductor (CMOS) field effecttransistor formed on a substrate using a method, comprising: (a)providing a substrate; (b) providing on said substrate a polysiliconlayer formed upon a gate dielectric layer of a gate structure of thetransistor; (c) doping the polysilicon layer using at least one dopant;(d) forming a polysilicon gate electrode of the gate structure; (e)depositing on the polysilicon gate electrode at least one of a metal andan alloy; and (d) siliciding the polysilicon gate electrode to form asilicide adjacent to said gate dielectric layer.
 2. The transistor ofclaim 1, wherein the doping step (c) is performed after the forming step(d).
 3. The transistor of claim 1, wherein the at least one dopantcomprises at least one of As, P, B, Sb, Bi, In, Tl, Al, Ga, Ge, Sn andN₂.
 4. The transistor of claim 1, wherein the doping step (c) dopes thepolysilicon layer using only Sb.
 5. The transistor of claim 1, whereinthe doping step (c) dopes the polysilicon layer using an ionimplantation process.
 6. The transistor of claim 5, wherein the dopingstep (c) dopes the polysilicon layer using a pre-determined dose in arange from about 1×10¹⁴ to 4×10¹⁵ ions/cm².
 7. The transistor of claim1, wherein the forming step (d) further comprises the step of:amorphizing the polysilicon gate electrode.
 8. The transistor of claim7, wherein said amorphizing step comprises the step of: performing anion implantation process using at least one of Si and Ge.
 9. Thetransistor of claim 1, wherein said at least one of the metal comprisesat least one of Ni, Co, Pt, Ti, Pd, W, Mo, and Ta.
 10. The transistor ofclaim 1, wherein said at least one of the metal comprises Ni.
 11. Thetransistor of claim 1, wherein said at least one of the metal comprisesCo.
 12. The transistor of claim 1, wherein said at least one of thealloy comprises at least one of C, Al, Ti, V, Cr, Mn, Fe, Co, Ni, Cu,Ge, Zr, Nb, Mo, Ru, Rh, Pd, Ag, In, Sn, Hf, Ta, W, Re, Ir, and Pt. 13.The transistor of claim 1, wherein said siliciding step employs anannealing process.
 14. The transistor of claim 13, wherein the annealingprocess is performed at a substrate temperature of about 350 to 750degrees Celsius for a duration of about 0.3 to 30 min.
 15. Thetransistor of claim 13, wherein the annealing process forms at least onemonolayer of the at least one dopant at an interface between the gatedielectric layer and the silicide to control work function and electronmobility in the silicide.